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09-9721010
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איש קשר:
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רונית
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| דרישות: |
VERIFICATION Junior Engineer - Education: BSc in Electrical/Electronics/Computers engineering or BSc in Computer Science.
Experience: 2 and up years experience in VLSI design verification. Specman or System Verilog (as a verification language) - is a must.
Scripting language (perl, tcsh, bash, awk) is an advantage. Availability for traveling is an advantege.
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| היקף המשרה: |
מלאה |
עיר/ישוב: |
הרצליה |
תפקיד: |
איש צוות |
שנות ניסיון: |
שנתיים |
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