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| טל: |
09-9721010
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איש קשר:
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Ronit
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| תיאור: |
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Senior Verification Engineer
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| דרישות: |
Education: BSc in Electrical/Electronics/Computers engineering or BSc in Computer Science.
Experience:
5 and up years experience in VLSI design verification projects.
Specman or System Verilog (as a verification language) - must.
Familiarity with latest EDA technologies and methodologies such as: OVM, VMM, Vmanager, IVB, etc - Required.
Scripting language skills (perl, tcsh, bash, awk) is a must.
Verification environment architecture experience - major advantege.
Verification team leading experience - major advantage.
Availability for traveling is an advantege.
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| היקף המשרה: |
מלאה |
עיר/ישוב: |
הרצליה |
תפקיד: |
מנהל צוות |
שנות ניסיון: |
5 שנים |
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